Particular embodiments generally relate to circuit design automation tools, and more specifically to clock tree synthesis analysis tools.
Design automation tools allow integrated circuit (IC) (“chip”) or board-level designers to implement increasingly complex designs. One such automation tool is a clock tree synthesis (CTS) tool that can balance and route a clock signal to very large numbers of registers, gates, circuits, etc., while optimizing for skew, capacitance, signal slew rates, and other factors. However, conventional graphical user interfaces (GUIs) for analyzing CTS results are limited.